Bharat Londhe

About Bharat Londhe

TECHNICAL SKILLS :Full Chip SCAN and SMS planing, Integration & Verification.SCAN Insertion.ATPG - Stuck-at, At-speed, IDDQ, SDD.SCAN Coverage Analysis and Improvement.LOES SCAN Implementation.LogicVision Memory BIST.Synopsys SMS 5.x, 6.x Memory BIST.SCAN, MBIST, IP Timing Constraints for PD and STA.Gate Level formal verification (LEC).SCAN Clock Planing.Test Mux RTL and Hook-up.IP Test Wrapper - PCIE2, PLL, ADC, EFUSE.Parametric IO tests.Gate level Timing and No-timing Simulations.Utility Development Using PERL.Verilog Coding.JTAG, Boundary Scan.Core Wrapping.Scan Pattern Porting/Merging/DemergingPython, Perl, Tcl based file processing.Silicon bringup.

Experience

1. Principal Engineer

   Marvell Technology

   Nov 2024 — Present · Pune, IN

Education

• SSGM College, Kopargaon

  Bachelor's degree, Electronic Science

• Department Of Electronics Science,University of Pune

  Master's degree, Electronic Science

  2010 — 2012

Skills

• Rtl Design
• Static Timing Analysis
• Jtag
• Vlsi
• Perl
• Wgl
• Tcl
• Semiconductors
• Dft
• Systemverilog
• Atpg
• Mbist
• Asic
• Lec
• System on a Chip (Soc)
• Very-Large-Scale Integration (Vlsi)
• Automatic Test Pattern Generation (Atpg)
• Bscan
• Sta
• Testing
• Scan
• Verilog
• Application-Specific Integrated Circuits (Asic)
• Soc
• Gls