Bharat Kumar Jangid
PD Integration Engineer at Intel
- Role
- Physical Design Integration Engineer at Intel
- Location
- Jaipur, RJ, IN
- LinkedIn followers
- 500 followers
About Bharat Kumar Jangid
I am a Physical Design Integration Engineer at Intel, with 2+ years of experience in semiconductor industry. I am responsible for TestChip/ FullChip Development and Integration. I work on FullChip layout collateral construction automation using cadence virtuoso SKILL and full chip design verification using Synopsys ICV/ Calibre DRV. My work includes collaboration and communication with Onsite/ Cross site teams for delivering the FullChip on time with quality.My core competencies include FullChip Integration and Layout generation using cadence virtuoso, layout automation using SKILL, layout DRC signoff using Cadence Virtuoso/ Synopsys ICV/ Calibre DRV. I have successfully taped-in multiple fulchip layouts, supported onsite/cross site teams for content closer for fullchip delivery on-time with quality.
Experience
Physical Design Integration Engineer
Nov 2023 — Present · Bengaluru, IN
Education
Poornima Institute of Engineering & Technology
Bachelor of Technology - BTech, Electronics and Communication
2011 — 2015
National Institute of Technology Hamirpur-Alumni
Master of Technology - MTech, VLSI
2017 — 2019
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.