Bharadwaj Tigulla

About Bharadwaj Tigulla

Ph: 09•••••••68Email: b••••••••@gmail.com,Experience of over 10 years in ASIC/FPGA front end RTL design involving micro architecture, design, execution, and debugging issues at IP and Subsystem level. Hands on experience in ARM coresight 400 based Debug/trace designs and execution of SMMU500 and various functional IPs. Expertise in CDC, Linting, low power design and STA methodologies and tools. Hands on experience in solving functional and execution issues at IP/sub system/tile level. Specialtities-> Proficiency in Verilog/system verilog-> Micro Architecture, design and Debug for ARM Coresight 400 and ARM based designs -> Hands on experience in debug/trace/trigger designs and proprietary IPs-> PPA aware design proposals with minimal functional changes-> Expertize in CDC(spyglass), STA, Synthesis(Design compiler),Linting, Low power Design methodologies for IP/subsystem -> proven track record of successful project execution and releases and sign-off activities at Subsystem/SOC level issues-> System verilog Assertions-> Good Digital logic skills-> scriting languages like shell and perl-> Good programming skills in C-> Good written and verbal communication skills.BHARADWAJ.T

Experience

1. Staff Engineer

   Qualcomm

   Dec 2025 — Present

Education

• Jawaharlal Nehru Technological University

  Master of Science (MS), VLSI

  2010 — 2012

• Jawaharlal Nehru Technological University

  Master's degree, VLSI

  2010 — 2012

Skills

• Debugging
• Systemverilog
• Sv Assertions
• Vcs
• Static Timing Analysis
• Synopsys Tools
• Linting
• Spyglass
• Clock Domain Crossing
• Chipscope Pro
• Cmos
• Vlsi
• Assertions
• Veritas Cluster Server
• Logic Synthesis
• Rtl Coding
• Rtl Design
• C
• Cdc
• Xilinx Ise
• Verilog
• Fpga
• Asic
• Physical De
• Perl