Bhadresh Patel
Senior Post Silicon Validation engineer
- Role
- Senior Silicon Validation Engineer at Lattice Semiconductor
- Location
- Mahesana, GJ, IN
- LinkedIn followers
- 500 followers
About Bhadresh Patel
1> Hardware ArchitectureProtocol validation ( PCIe Gen5 & Gen6, USB 3.2)2> Component selection3> Schematic design & Pcb layout review4> High-speed board design PCIE 5.0,and PCI 6.0, DDR3,USB 3.0, Ethernet.etc5> Board debugging and validation report6> Production document 7> c language8>Low power board design9) FPGA Based High speed Board 10>signal integrity report validation11) Power integrity and signal integrity 12) 64GHz and 33GHz Real Time scope 13) S parameter analysis - Embedding and Deembedding for s parameter in frequency domain14 ) Jitter analysis 15) Eye Diagram Analysis 16 ) root cause analysis of signal integrity family
Experience
Senior Silicon Validation Engineer
Apr 2025 — Present · IN
Education
Ahmedabad Institute Of Technology
Bachelor's degree, Electrical, Electronics and Communications Engineering
2012 — 2016
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