Beraa Tafech
Physical Design - Project Engineering Manager, Solutions Group (Sg) @Synopsys Inc
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WORK HISTORY
Physical Design - Project Engineering Manager, Solutions Group (Sg) @Synopsys Inc
Burnaby, BC, CA
Supporting marketing and sales teams win projects & enable customer SOCs using Synopsys IP (DDR PHYs) • Analyzing customer’s requirements and proposing solutions in terms of floorplan, bump map, design for test features, packaging and silicon technology • Upon finalizing a solution, oversee their execution through all the development stages until delivery and integration into customer’s SOC or ASIC • A trusted advisor to both internal and external design teams • Working with cutting edge technology and advanced packaging from tier one silicon foundries and semiconductor manufacturers, as well as the top technology companies in the world working on SOCs and ASICs • Serve as a conduit into IP R&D of ideas for product improvement based on actual implementation experience • Write project documentation, conduct phase reviews, certify checklists
EDUCATION
École Secondaire Moscrop Secondary School
High School Diploma, Grades 8-12
The University of British Columbia
Bachelor of Applied Science, Computer Engineering
The University of British Columbia
Master of Engineering - Engineering Management Sub-Specialization, System on Chip (SoC)
ABOUT BERAA TAFECH
A proactive, organized, and focused leader with extensive technical and project management experience and a track record of driving internationally-dispersed and culturally-diverse teams to successful project execution. Over 15 years technical experience and ASIC/SoC project management. Successfully led projects throughout the entire project lifecycle, while achieving quality deliverables and ensuring adherence to best practices and established processes. Experience includes managing multiple high-impact projects for a Fortune 100 company and coordinating the efforts of local and virtual teams consisting of both full time-staff and contractors dispersed across various American and Canadian cities, Malaysia, India, and Egypt. Technical experience includes: full chip layout lead, full chip STA lead, DFT architecture, synthesis, and ARM cores (RTL-to-GDSII expertise). I am a motivated, highly-organized leader with a “can do attitude” and place a strong focus on customer satisfaction. I view challenges as opportunities and always on the lookout to improve and enhance existing processes/standards and best practices to improve efficiencies and the organization’s bottom line. “Impossible is just a big word thrown around by small men who find it easier to live in the world they’ve been given than to explore the power they have to change it. Impossible is not a fact. It’s an opinion\" Muhammad Ali
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