Bibekananda P.

About Bibekananda P.

7+ Years of experience in Physical Design and Signoff. Worked on multiple Physical Design domains with proven track record of delivering exceptional results.** Looking for Challenging Work **. Hands-on experience in full closure of high frequency, high compute, PPA critical, hierarchical, million gate designs (2-6M) staring from physical synthesis to GDS. Experience of working as PD owner in both Google Cloud TPU, CPU and Google Pixel TPU. Hands-on experience in closing various PDN sign-off checks - Static, Dynamic, EM (Power and Signal) at block and IP level Hands-on experience in IP level Bump Planning and Bump Assignment, Macro Resistance Sign-off, ESD Checks, Inrush Analysis and CPM Analysis. While working at Cypress Semiconductor, worked on Logic Equivalence Check, Low Power Static Check (Primarily) along with IR and Power Analysis (PTPX). Good understanding of Low Power Design, Physical design stages, STA etc. Basic understanding of DFT flow, Scan, ATPG (learned during training at Cypress and while interacting with DFT engineers for LEC, CLP and IR). Passionate about Analog/Circuit Design (Explored the Analog Domain while doing Masters at BITS Goa. Worked on Sigma Delta ADC). Eager to explore understanding of underlying mechanism of different EDA tools used in VLSI backend and improve using machine learning. ML EDA, EDA ML, AI for EDA

Experience

1. Silicon Engineer

   Google

   Feb 2021 — Present · Bengaluru, IN

   Physical Design- PD Implementation of various blocks part of Google Cloud TPU/CPU- PD Implementation and all signoff convergence of two generations of Pixel Tensor TPU Sub Block PDN/EMIR- EMIR Signoff Owner for two generations of Pixel Tensor GPU subsystem.

Education

• Birla Institute of Technology and Science, Pilani

  Master of Engineering - MEng, Microelectronics

  2016 — 2018

• Kalyani Government Engineering College

  B. Tech, Electronics and communication

  2010 — 2014