Akshay B.
HDL(Verilog) || Studious
- Role
- Gpio Layout Design Engineer at 铿腾设计系统公司
- Location
- Tirupati, AP, IN
- LinkedIn followers
- 500 followers
Experience
Gpio Layout Design Engineer
Sep 2025 — Present · Hyderabad, IN
Education
Sree Vidyanikethan Engineering college, Tirupati
Bachelor of Technology - BTech, Electronics and Communications Engineering
A. P. MODEL SCHOOL
Secondary Education., SSC
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