Akhil Batchu
Verification Engineer at Scaledge Technology| SV | UVM | CRV | ABV | VCS | Verdi for Ex- Synopsys India Pvt. Ltd. || Ex-Velodyne Lidar || Ex-Accenture Solutions Pvt. Ltd.
- Role
- Verification Engineer at Scaledge Technology
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Akhil Batchu
I am an experienced IP functional verification engineer with ~3 years of hands-on expertise in IP functional verification using SystemVerilog/UVM, functional coverage, and assertions.I have verified UniPro protocol IP, built reusable UVM testbenches, and automated verification flows for high productivity and to have a scalable regression environment. My verification approach emphasizes protocol correctness, coverage completeness, and efficient debug.My core strengths include the following:Tools used: VCS, Verdi - To ensure that the tools are used to analyze the waveform and debug and classify it whether is a design issue or a testbench issue and fix it to make it more and more robust.Scripting: Python, Perl, Shell - To ensure the regression is automated and currently it has reduced the overall regression time to around 40%, making it reliable and scalable regression environment.CAD Infrastructure: IBM Load Sharing Facility (LSF)- To ensure that the testcases are run with slots sufficient enough to run the testcases faster and run the regressions in a smoother way.Skills: Functional Coverage, Constraint Random Verification (CRV), Assertion Based Verification (ABV)- To ensure that the functionality of the design in all aspects is/are covered, and also ensured that the assertions are written to check if the designs behavior is as per the expectation or not, thereby finding the design bugs at an early stage.Also, I worked closely with the design team to generate some more corner scenarios which they saw as important to fix it.I’m actively exploring opportunities where I can work in deep into the design functionality and develop all kinds of scenarios (including corner scenarios) and also go in deep into the verification plan for an entire feature, to ensure that the feature is exercised across all possible scnarios for a robust RTL design and drive high-quality design delivery. Feel free to reach out!
Experience
Verification Engineer
Mar 2026 — Present · Hyderabad, IN
Education
Sri Chaitanya Junior College, Habsiguda
Intermediate, Pre-Engineering
2014 — 2016
Kendriya Vidyalaya No. 2 Uppal
High School
CVR College of Engineering, Hyderabad
Bachelor of Technology - BTech, Electronics and Communication Engineering
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