Bastien Giraud

Memory Design Research Engineer in Advanced Technologies @CEA

Lyon, FR
MOBILE NUMBERS
+91 *********19

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WORK HISTORY

Apr 2010 — Present

Memory Design Research Engineer in Advanced Technologies @CEA

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Low power digital and SRAM circuit design in BULK and fully depleted SOI technology (28nm & 14nm)- Study of novel FDSOI device architectures- Design of innovative digital and SRAM circuits in sub-32nm FDSOI technology- Industrial Design Platform porting from BULK to FDSOI, leading to strong interactions with process, device, cad2mask, DK, SRAM and digital design teams- SRAM memory and Standard cell characterization in 28nm FDSOI technologyStrong collaboration with STMicroelectronics and IBM allianceInnovative SRAM cut operating in specific environmentNon volatile memory cut and crossbar using ReRAM technologies such as OxRAM and CBRAM.15 strategic patents on memory design

SKILLS

Memory CharacterizationMemory DesignLow-Power DesignMemory TestEnergy EfficiencyAnalog Circuit DesignDigital Ic DesignCharacterizationCadence VirtuosoCmosFdsoiLow VoltageStandard Cell CharacterizationVariation AnalysisProject ManagementAdvanced TechnologiesLow Power DesignUltra Wide Voltage RangeSramSoi

ABOUT BASTIEN GIRAUD

Research Engineer in Memory Circuit Design

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Bastien Giraud — Memory Design Research Engineer in Advanced Technologies at CEA in Lyon, FR | Unifers