Basavaraja P M
🎓2025 ECE Graduate | VLSI Design and Verification Trainee | RTL Design | Skilled in Verilog, System Verilog, SVA, UVM | PCIe, APB, UART | Linux | C, Python.
- Role
- Design and Verification Trainee at Vlsi First
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Basavaraja P M
Design and Verification Engineer (Fresher) with strong expertise in RTL Design and UVM-based Functional Verification using Verilog and SystemVerilog, with hands-on experience in assertions, coverage, simulation, and waveform debugging for robust design validation, along with exposure to end-to-end verification flow including test planning and bug debugging; prepared to deliver high-quality, silicon-ready designs in fast-paced VLSI environments.
Experience
Design and Verification Trainee
Jun 2025 — Present · Bengaluru, IN
Currently undergoing hands-on training in VLSI Design and Functional Verification.• Learning SystemVerilog, UVM (Universal Verification Methodology), and testbench architecture.• Gaining exposure to simulation tools and real-time verification projects.• Building a strong foundation in digital design concepts and verification methodologies.• Aiming to become an industry-ready Verification Engineer in the semiconductor domain.
Education
AMC Engineering College
Bachelor of Engineering - BE, Electronics and Communications Engineering
Prarthana High School
SSLC
Science Academy PU College
2nd PUC, Science - PCMB
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