Bartolome Jr Ebalobo
Senior Analog and Mixed-signal Ic Layout Engineer @Renesas Electronics
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WORK HISTORY
Senior Analog and Mixed-signal Ic Layout Engineer @Renesas Electronics
Harlow, GB
Executed chip-top and block-level analog/mixed-signal layout designs across multiple technology nodes (350nm → 40nm) using leading foundries including TSMC, GlobalFoundries, Dongbu HiTek, Vanguard International Semiconductor, and X-FAB, ensuring robust DRC/LVS closure and high manufacturability across legacy and mature nodes.Delivered automotive and industrial-grade IC layouts in TSMC 180nm BCD Lite and BCD 100V technologies, supporting high-voltage and mixed-signal applications with strong focus on reliability (ESD, latch-up, EM) and long-term product qualification.Contributed to advanced-node mixed-signal SoC development in TSMC 22nm, enabling high-performance, area-optimized layouts and supporting complex chip integration requirements.
EDUCATION
Technological Institute of the Philippines
Bachelor's degree, Electronics and Communications Engineering
ABOUT BARTOLOME JR EBALOBO
Staff / Principal Analog IC Layout Engineer with 19+ years of experience delivering production silicon across CMOS and advanced FinFET technologies (350nm → 14nm). My work focuses on the physical implementation & integration of Power Management (PMU), RFIC and Mixed-Signal analog IP within complex SoCs.I specialize in translating schematic intent into robust manufacturable layouts for high-performance analog circuits, ensuring verification closure, parasitic optimization & reliable silicon performance across multiple tape-outs.Throughout my career I have owned & implemented critical analog layout blocks across three primary domains:Power Management (PMU) • LDO regulators • Charge pumps • Switching regulators • Bandgap references • Power routing and decoupling strategies for mixed-signal environmentsRFIC Layout • LNAs, mixers, oscillators & RF amplifiers (up to 60 GHz) • Shielded routing and differential symmetry for RF signal integrity • Parasitic control & substrate noise mitigationMixed-Signal SoC Integration • PLL subsystems including VCO, charge pump & loop filter • ADC/DAC interfaces and precision analog front-ends • Mixed-signal SoC floorplanning with analog/digital isolation strategiesI have delivered production silicon across multiple leading foundries including TSMC, GlobalFoundries, UMC, X-Fab, Vanguard & ROHM, supporting mixed-signal SoCs integrating RF, PLL, ADC/DAC & PMU subsystems.Core technical strengths include:• PMU analog layout & power distribution strategies • RFIC layout methodologies for high-frequency circuits • Mixed-signal SoC floorplanning & substrate noise isolation • Advanced node layout including FinFET technologies and LDE mitigation • Full physical verification flow including DRC, LVS, ERC, PERC, EM/IR and DFM • Cross-functional collaboration with circuit designers, CAD teams and system architects • Driving layout quality through peer reviews & tape-out readinessI have contributed to multiple successful silicon tape-outs across technology nodes from 350nm to 14nm FinFET, supporting RF communication systems, power-management solutions & complex mixed-signal SoCs.Currently based in the United Kingdom with previous engineering experience in Germany. I hold an EU Blue Card and am open to Staff / Principal level opportunities across Europe involving advanced analog layout, PMU development, RFIC implementation & mixed-signal SoC integration.Always open to connecting with engineers, hiring managers & technical recruiters working on next-generation semiconductor technologies.
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