Bandaru Venkatesh
Formal Verification Engineer @Google
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WORK HISTORY
Formal Verification Engineer @Google
Bengaluru, IN
EDUCATION
Indian Institute Of Information Technology Allahabad
Bachelor of Technology (B.Tech.), Electronics and Communications Engineering
Sri Chaitanya Junior College
intermediate, MPC
Hayathnagar public school
10th class, High School/Secondary Certificate Programs
ABOUT BANDARU VENKATESH
I am a Formal Verification Engineer and a silicon perfectionist, specializing in mathematical methods to ensure architectural correctness in complex hardware designs.My focus is on tackling deep-bound bugs that are undetectable by traditional simulation. I leverage Formal Verification techniques to build confidence in the silicon that powers devices like the Google Pixel.Core Technical Expertise:Formal Verification of Caches and out-of-order coresWriting assertion-based verification testbenches and formal modelsExpertise in E2E checks, formal abstractions, and convergencePreviously, I contributed to critical IP verification at Arm (Vector Processing Unit) and Intel(Caches and schedulers ). I believe verification is about guaranteeing design behavior, not just debugging RTL.I even presented my approach in a paper titled \"Uncovering deep bound bugs: FV with a Cape\" at the Cadence Club Formal India and Intel FV Global Summit.
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