Balram Bansal

About Balram Bansal

Passion of learning and exploring the things.Specialties: SoC EMIR and Physical Verification, Custom Layout, Analog Circuit design, STD cell and Automation.Handling full SoC Physical Integration, PV and PDN sign-off. Good Knowledge of custom, IO/Analog layout and Small Design circuit design.Working on SoC physical Verification and chip finishing checks. This includes PERC, LVS, DRC, ERC, LFD, DFM, CMP, PM, ESD/LUP Checks and other chip sign off CALIBRE based checks. Working on EMIR (Vector-less and vector based) analyses, B2C analyses, optimizing Power grid, improving flow and methodology.Technology Worked on 130nm, 90nm,65nm, 55nm, 40nm, 28nm CMOS, 45FDSOI, 40TFS and 14finfet, 11lpp, 10finfet, 8lpp, 7ff, 5nm and 4nm.Collaborating across the team to get data for Physical Verification(PV) and PDN and give them feedback.Set the guidelines from PV and PDN perspective for different teams to ensure smooth closure. Collaborating with IP owners for the closing PERC, ERC and DRC at SOC level in terms of waivers.Writing scripts and modifying existing scripts to get the work done. These codes include SVRF, SKILL, PERL, Shell, Calibre DRV, TCL and Python.Very good debugging skills. Good knowledge of ESD/LUP concept.Use PNR tool to debug issues related to Physical Verification.

Experience

1. Sr Principal Engineer

   NXP Semiconductors

   Jul 2022 — Present · Bengaluru, IN

   Leading PDN and PDV Team along with improving efficiency using automation.

Education

• Pratibha Vikas Vidhalaya

  Senior Secondary Education, high school

  1999 — 2001

• Pusa Polytechnic

  Diploma, Electronics & Communication

  2001 — 2004

• Institute of Engineers

  B.Tech, Electronics & Communication

  2008 — 2010

• Govt. Co-edu Secondary School

  Secondary Education, High School

  1995 — 1999

Skills

• Lvs
• Drc
• Ic
• Design Rule Checking (Drc)
• Layout Versus Schematic (Lvs)
• Soc
• Cmos
• Asic
• Integrated Circuit Design
• Physical Design
• System on a Chip (Soc)
• Analog Layout
• Analog Circuit
• Physical Integration
• Semiconductors
• Floorplanning
• Vlsi
• Perl
• Eda
• Tcl
• Physical Verification
• I/O Layout
• Cadence Virtuoso