Balasubrahmanya K

About Balasubrahmanya K

10+ years of experience in RTL design- Hands on in Front End RTL design, FPGA design, algorithm development in C- Experience in SoC and IP implementation- Good understanding of video concepts and standards- Worked on Video Codec IP (H264 and H265) development, Display controller- Ability to develop test bench and verify/debug the design- Strong Analytical and Problem solving skills- Familiar with Xilinx ISE and Vivado, Altera Quartus, Modelsim tools.Graduated from Sri Jayachamarajendra College of Engineering, Mysore, under Electronics and Communication Engineering, in 2013.

Experience

1. Staff Engineer

   Qualcomm

   Dec 2024 — Present · Bengaluru, IN

Education

• Sri Jayachamarajendra College of Engineering, Mysore

  Graduation(B.E), Electronics and Communication Engineering

  2009 — 2013

Skills

• Algorithms
• Video Codec
• Vlsi
• C
• Xilinx Vivado
• Verilog
• Rtl Design
• Static Timing Analysis
• Rtl Coding
• Xilinx Ise
• Electronics
• Rtp
• Matlab
• Hevc
• Vhdl
• Tcl