Balasetty Sravani
Trainee Engineer - Physical Design | Trained in Physical Design | Digital Electronics | ASIC | CMOS | Fresher | Actively seeking opportunities
- Role
- Trainee Engineer - Physical Design at MosChip®
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Balasetty Sravani
Worked on 45nm technology node in making Layouts for Standard Cells( Inverter, Nand, And, Nor, Or, Mux, Ex-nor) by using fingering concept to some cells in Cadence virtuoso Layout L.I have hands-on exposure to the VLSI Physical Design flow, including synthesis, floorplanning, placement, clock tree synthesis, routing, and static timing analysis. As a fresher, I am passionate about learning and applying these skills to real-world chip design challenges.
Experience
Trainee Engineer - Physical Design
Nov 2025 — Present · Hyderabad, IN
Starting my career in Physical Design Domain.
Education
Prasad Concept School
SSCE
Sir M Visvesvaraya Institute Of Technology
Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering
Narayana Junior College - India
Mpic
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