Balakrishna C

About Balakrishna C

Experience in PNR & STA on the latest technologies of 3nm,5nm,7nm,10nm,16nm,28nm, 40nm and 65nm with multi-million gate design tape outs.~ Expertise in Functional & DFT SOC timing analysis and sign off.~ Expertise in Debugging and writing the Timing constraints.~ Hands on Experience in full Physical Design flow from Netlist to GDSII.~ Successfully implemented the A53 ARM core in 16nm.~ Experienced in Implementing DDR IP’s Hardening.~ Good understanding and knowledge on all aspects of backend ASIC design flow like Floor-planning/Power-planning, Place & Route, Clock Tree Synthesis, Timing closure, Signal Integrity Analysis, Static IR Drop Analysis, Formal Equivalence Check(Formality), and Physical Verification (DRC/LVS).~ Having experience in SOC level CTS building.~ Hands on experience in SOC level timing sign-off in hierarchal and flat mode.~ Good expertise in implementing the functional eco’s before and after the Base tapeout.~ Involved in Mutiple Tapeout’s and successfully working first Silicon.~ Expertise in TCL, perl, shell and Python.EDA Tools Expertise:~ ICC2, ICC, Innovus, Encounter~ Prime Time PT-SI, Tempus, Time Vision.~ StarRC, Quantus RC~ LEC, Formality~ Conformal LP~ Redhawk~ Scripting: TCL, db scripting, Perl, Shell, Python

Experience

1. Principal Engineer

   Marvell Technology

   Apr 2023 — Present

   Full Chip Timing Analysis and signoff for Functional and DFT Modes.* Debugging and writing the timing constraints.* Physical Design Block Level implementation.* Timing flow updates. Writing utility and analysis scripts.* Clock tree quality checking* Crosstalk issues.* CDC Timing * Generating timing ECO’s* Leading the teams towards Timing checklist Sign off for the Tapeout.* Coordinating the PD, STA and DFT teams for the suitable & quick timing fixes.Tools: PT-SI, Innovus, Tempus

Education

• National Institute of Technology, Tiruchirappalli

  M.Tech, VLSI Systems

  2007 — 2009

• JNTU Hyderabad

  B.Tech, EIE (Electronics and Instrumentation Engineering)

  2002 — 2006

• BSM ZPH school

  SSC, Xth class

  1999 — 2000

• Sri Adarsha Junior college

  Intermediate, MPC

  2000 — 2002

Skills

• Clock Tree Synthesis
• Mixed Signal
• Timing Closure
• Floorplanning
• Power Analysis
• Static Timing Analysis
• Synopsys Tools
• Lvs
• P&R
• Tcl
• Low-Power Design
• Very-Large-Scale Integration (Vlsi)
• Cts
• Application-Specific Integrated Circuits (Asic)
• Signal Integrity
• Physical Verification
• Physical Design
• Place & Route
• Timing