Balakrishna K
SoC DFT Design
- Role
- Soc Dft Lead at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Balakrishna K
Expertise in all aspects of DFX - Architecture, Scan planning, RTL/gate DFT, BSCAN & BIST Insertion, memory tests, ATPG, pattern validation, Silicon Debug. Thorough work experience in DFX for various High performance and low power SoC/IPs across process nodesHands-on experience in SoC RTL Integration, hook-up Verification and basic STA with good understanding of PD conceptsLead / managed dft teams that executed end to end DFX for complex SoCs, one of which includes automotive features like POST / in-system test requirements etc
Experience
Soc Dft Lead
Jan 2024 — Present
Education
National Institute of Technology Warangal
Bachelor of Technology (B.Tech.), Electronics and Communications
2001 — 2005
Manipal Academy of Higher Education
Master's degree, MicroElectronics
2012 — 2014
Skills
- Soc
- Vhdl
- Semiconductors
- C
- Formal Verification
- Rtl
- Jtag
- Automatic Test Pattern Generation (Atpg)
- Soc Rtl
- Atpg
- Dft
- Verilog
- Si Debug
- System on a Chip (Soc)
- Bist
- Perl
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