Balaji Upputuri

About Balaji Upputuri

Technical Skills: DFTAreas of Expertise: 1. DFT planning and Insertion for full chip design - Massive Network chips and ARM based SoCs2. Scan Design (Both LSSD & MUXed Scan) and Scan Compression techniques including Adaptive Scan, OPMISR/OPMISR+, Hybrid compression.3. Hierarchical Test implementation for larger size designs for core based design DFT flow.4. Logic BIST insertion, verification/simulations5. Memory BIST insertion and verification6. STA constraints review and support/ Reports analysis for DFT related testmodes7. JTAG (1149.1) and ACJTAG (1149.6).8. Transition and Path Delay Testing.( Both LOS and LOC)9. Running NC sim simulations/debug for all DFT tests (with/without SDFs).10. Production test support - preparation of test plans & test vectors, test coverage improvement, post Silicon Debug.11. Boolean equivalence check (Cadence Conformal-LEC), ECOs implementation with Test hook ups, Confomal ECO flow.12. IP testing, writing ICL and PDL for complex IPs SERDES/HBM/PCIE pseudo functional Tests.13. Verilog Test benches, tcl, perl scripts.14. Expert in IJTAG simulation debug15. Expert in Hierarchical simulation setup for running Zero/Timing Simulations to reduce TAT and improve overall efficiencyLeadership and Team Building Skills:1. Have lead DFT activities for High Speed Serdes cores and Memory Interface2. Experience in team building and mentoring3. Experience of working with teams across geographiesInnovation:1. Lead inventor of 6 patent application filed in USPTO2. Co-inventor of a 2 patent applications filed in USPTO3. Author of 3 publications related to DFT TAT reduction and reducing test logic burden on Functional timing.4. Co-author for few more publications related to Test power reduction & different scan compression techniques.5. Multiple Trade secretsSpecialties: Full Scan, Scan Compression, ATPG, LBIST, MBIST, Post Silicon Debug

Experience

1. Sr Principal Engineer

   Marvell Technology

   Apr 2023 — Present · Bengaluru, IN

Education

• VEDA IIT - Hyderabad

  Diploma in Advanced VLSI design, VLSI

  2004 — 2005

• Damodara Residential School, Ongole, AP

  10th Class, ONGOLE

• Board of Intermediate Education

  Intermediate, Maths, Physics and Chemistry

  1997 — 1999

• Jawaharlal Nehru Technological University

  Bachelor of Technology - BTech, Electronics and Communications Engineering

  2000 — 2004

Skills

• Asic
• Dft
• Debugging
• Ncsim
• Atpg
• Jtag
• Memory Bist
• Bist
• Verilog
• Vhdl
• Soc
• Static Timing Analysis
• Vlsi
• Functional Verification
• Tcl
• Testing
• Eda
• Rtl Design
• Semiconductors
• Systemverilog
• Ic
• C
• Embedded Systems
• Perl
• Tcl-Tk
• Application-Specific Integrated Circuits (Asic)
• System on a Chip (Soc)
• Automatic Test Pattern Generation (Atpg)
• Very-Large-Scale Integration (Vlsi)
• Semiconductor Industry
• Digital Electronics
• Joint Test Action Group (Jtag)