Balaji Janapala

About Balaji Janapala

Qualcomm\'s SOC validation team benefits from over a decade of expertise in hardware and software testing, with a focus on Memory/DDR subsystems. Contributions include developing DDR-centric system-level content in C, debugging using T32, and enabling Memory IP workloads across diverse chipset segments like mobile, auto, XR, and compute. Teams are empowered to implement robust debugging practices and enhance concurrency validation processes. Prior roles at Intel and Qualcomm emphasized SOC-wide validation, power state analysis, and automation using PERL and Python. Key achievements include supporting chip power-on activities and leveraging tools like oscilloscopes and logic analyzers for hardware-level debugging. Known for an analytical approach and a deep understanding of SOC architectures, work is driven by a commitment to delivering reliable, high-performance silicon for cutting-edge applications.

Experience

1. Senior Staff Engineer

   Qualcomm

   Aug 2021 — Present · Bengaluru, IN

   Leading a team of 4 engineers and Responsible for Memory IP content Development, enablement and debug on multiple segments of qualcomm chipsets like Mobile, Auto, XR and Compute.2. Well versed with different debugging techniques using Jtag(Trace32), HW events and driver logs.3. Content Development in C language.4. DDR centric System level content development for concurrency use cases.5. Responsible for Customer RMA issues debug

Education

• Jawaharlal Nehru Technological University

  Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering

  2006 — 2010

Skills

• Embedded Linux
• Perl Script
• Perl Automation
• Device Drivers
• Debugging
• C Language
• Test Automation
• Embedded C
• Testing
• Arm
• Real-Time Operating Systems (Rtos)
• Perl
• Embedded Systems
• Embedded Software
• Test Planning
• Rtos
• C
• Linux Kernel
• Linux
• Slimbus, I2c, Spi,Data Movers,Adc
• Regression Testing