Bahubali Babagond

Manager, ASIC (IC) Engineering @ Renesas Electronics | DCDC Converters, RF

Role
Manager, Asic (Ic) Engineering at Renesas Electronics
Location
Santa Clara, CA, US
LinkedIn followers
500 followers

About Bahubali Babagond

I am a Manager ASIC (IC) Engineer at Renesas Electronics, a leading provider of advanced semiconductor solutions, with over 20 years of industry experience. I hold a B.E. degree in Electronics and Communication Engineering and have expertise in power FET design, power management IC layouts, and analog and RF layout design across various process technologies.Throughout my career, I have successfully executed the layout and integration of full-chip designs for DC-DC converters, charge pumps, MLC, buck-boost regulators, direct chargers, and linear chargers, utilizing state-of-the-art tools and methodologies. Additionally, I have led and managed teams of over 15 engineers, providing training, mentorship, and strategic guidance on layout design methodologies.I am committed to delivering high-quality, efficient layouts that align with customer requirements and company standards. Passionate about innovation, I continuously seek opportunities to expand my skill set, adopt emerging technologies, and collaborate with industry experts. My objective is to drive technological advancements and contribute to the continued success of Renesas Electronics and the semiconductor industry.

Experience

  1. Manager, Asic (Ic) Engineering

    Renesas Electronics

    Apr 2025 — Present · US

    Custom PMICs and high-efficiency power converters for consumer electronics.

Education

  • Vishweshwaraiah Technology University

    BE, Electronics and Communication

    2002 — 2005

  • JNV Alamatti Bijapur Dist.

    PUC, Science

    1993 — 2001

Skills

  • Floorplanning
  • Design Rule Checking (Drc)
  • Drc
  • Asic
  • Pll
  • Rf
  • Radio Frequency (Rf)
  • Parasitic Extraction
  • Esd and Latchup
  • Rf Mask Design
  • Very-Large-Scale Integration (Vlsi)
  • Cmos
  • Verilog
  • Eda
  • Mask Design
  • Soc
  • Substrate Noise Analysis
  • Rc Extraction
  • Physical Design
  • Layout Versus Schematic (Lvs)
  • Analog
  • Lvs
  • Cadence Virtuoso
  • Vlsi
  • Application-Specific Integrated Circuits (Asic)
  • Physical Verification
  • Power Management
  • Mixed Signal
  • System on a Chip (Soc)

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Bahubali Babagond — Manager, Asic (Ic) Engineering at Renesas Electronics in Santa Clara, CA, US | Unifers