Bache Rangaswamy

About Bache Rangaswamy

Overall 12+ years of experience in Physical Design across multiple tech nodes, like 3nm, 5nm, 7nm, 10nm, 12nm, 14nm, 90nm & 180nm• 8+ years in Marvell India pvt ltd, Bangalore as Senior Staff Engineer - PD• 1 year in Black Pepper Technologies, Bangalore as Senior PD Engineer• 1.5 years Intel India Pvt Ltd as PD Engineer• 1 year in Ministry of Electronics and Information Technology (MeitY) as Intern Analog PD Hands on experience to Full Chip level Partitioning, Placing & Port alignment for sub-chips & blocks, Clocking, Route & create ECO’s. Designed & Implemented custom clock trees including mesh networks and performed SPICE simulations for validation. Lead multiple complex low power projects along with implementation from RTL to GDS Expert in floor-planning, placement, clocking, routing, Signoff Timing closure (STA), ECO generation, Physical verification (DRC, LVS, ANT, ERC & PERC), Signal EM & IR (static & dynamic) drops fixes Hands on experience in tools like Innovus, Quntus, Tweaker, Tempus, Calibre, DC, ICC-II, StartRC, prime time, Voltus & Calibre Part of methodology development & own LVL placement procs Hands on experience at TCL & Perl scripting Overall have good experience from RTL to GDS Tools Used:Cadence Tools - Innovus, Quantus, Tempus, Conformal LEC, Conformal Low Power & VoltusSynopsys Tools - ICC, ICC-II, DC, StarXT, PrimeTime & IC ValidatorIntel Tools - Genesis Ansys - RedHawkMentor - CalibreTechnology Nodes:Realtime - 3nm, 5nm, 7nm, 10nm, 12nm & 14nmInternship - 90nm & 180nmResponsibilities:Current - Projects- Handling Full Chip & Clocking, was Leading the US project(3nm) from India with 15 members team which is covering complete backend work(Power(2), PSI(1), DFT(1) & PD(11)) along with owning of 5 blocks from netlist to complete GDS-II generation that includes all signoff checks & fixes. Methodology - Complete owning of 2 procs where I will create the proc in the methodology flow & keep on enhancing the proc based on project/technology requirements. Previous - Worked on 10 projects in 3 different companies with different technology nodes where my responsibilities are working on min 3 critical blocks in each projects taking through netlist to till GDS-II generation that covers all signoff checks and fixes

Experience

1. Senior Staff Engineer - Physical Design

   Marvell Technology

   Apr 2023 — Present · Bengaluru, IN

   Handling Full-Chip level (156mm^2) partitioning, placing, port alignment, feed-though planning, clocking, routing & signoff closure. It has 8 sub-chips and ~190 blocks. Regular sync ups with Packaging, Power, RTL & DFT teams to make sure things are aligned from Full Chip Level. Designed initial floorplan using visio tool for better understand based on connectivity & dataflow diagram.I was handling & leading one of the big partitions (~40% of FC, 6 sub-partitions & 35 standalone blocks) & Full-Chip clocking with MESH method. Timing challenges are the major, frequency is 1.6GHZ. In Sub-Chip block portioning, placement, port alignment, placing physical cells like Temperature Sensors, ESD & other DFM cells and pushing to block level. Handling from RTL – GDS, so interacting to respective RTL, DFT, POWER & STA teams with feedbacks to improve the designs.

Education

• Kottam college of Engineering

  Bachelor of Technology (B.Tech.), Electronics and Communications Engineering

  2008 — 2012

• National Institute of Technology, Tiruchirappalli

  Master of Technology (M.Tech.), VLSI Systems

  2012 — 2014

Skills

• Cadence Virtuoso
• Matlab
• Manufacturing
• Computer Language
• Microsoft Excel
• Modelsim
• C++
• Verilog
• Pspice
• Microsoft Word
• Microsoft Office
• Communication
• Xilinx