Kiran Kumar Azmeera
Lead RTL Design Engineer
- Role
- Lead Design Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Kiran Kumar Azmeera
RTL Design Engineer with hands-on experience in PCIe 6.0, SerDes, APB, LPDDR5, LPDDR5x and AXI protocols. Skilled in microarchitecture design, RTL coding, and functional verification. Proficient with tools like VCS, Design Compiler, and linting flows.Passionate about bridging complex digital protocols with efficient silicon-ready designs.
Experience
Lead Design Engineer
Jun 2025 — Present · Bengaluru, IN
Working on GDDR7, DDR5 and LPDDR5x, LPDDR6 PHY RTL Design and DFT RTL Design.
Education
RGUKT Basar
Six Years Integrated Engineering Course, Pre University Course (MPC) + Bachelor of Technology (ECE)
Indian Institute of Technology, Kanpur
Master of Technology (EE), Signal Processing & Communication, Networks
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