Ayushi Shrivastava

Senior Design Verification Engineer@Marvell | MNIT Jaipur | M.Tech VLSI Design (2023-2025)| Gate 2023 EC Score: 600

Role: Senior Design Verification Engineer at Marvell Technology
Location: Jaipur, RJ, IN
LinkedIn followers: 500 followers

EngineeringView LinkedIn profile

About Ayushi Shrivastava

I have completed an M.Tech in VLSI Design and a B.Tech in ECE with a minor specialization…

Experience

Senior Design Verification Engineer
Marvell Technology
Jul 2025 — Present · Pune, IN

Education

Malaviya National Institute of Technology Jaipur
Master of Technology - MTech
2023 — 2025
Manipal University Jaipur
B.Tech
2019 — 2023
St. Teresa's Sr. Sec. School, Jaipur (CBSE)
12th:95%(Science), 10th: 10 CGPA

Contact information

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•••••@marvell.com
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Current company

Marvell Technology

Semiconductor Manufacturing · 5K employees · Founded 1995 · 5488 Marvell Lane, Santa Clara, CA, 95054, US

We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, we go all in with you. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.

marvell.com

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About Ayushi Shrivastava

Experience

Senior Design Verification Engineer

Education

Malaviya National Institute of Technology Jaipur

Manipal University Jaipur

St. Teresa's Sr. Sec. School, Jaipur (CBSE)

Find verified contacts for anyone on LinkedIn