Ayush Singh
ASIC/FPGA Design Engineer at Ciena
- Role
- Asic Fpga Engineer 1b at Ciena
- Location
- Gurugram, HR, IN
- LinkedIn followers
- 500 followers
About Ayush Singh
My area of interest is Digital electronics, Verilog and Digital system design using HDL…
Experience
Asic Fpga Engineer 1b
Jan 2024 — Present · Gurugram, IN
Education
National Institute of Technology Calicut
Master of Technology - MTech
2020 — 2022
AJAY KUMAR GARG ENGINEERING COLLEGE, GHAZIABAD
Bachelor of Technology - BTech
2015 — 2019
City Montessori School
Intermediate
2013 — 2014
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.