Ayush Jain

About Ayush Jain

I am a SoC design Engineer at Intel corporation, having competent skills in VLSI design (frontend and backend), post-silicon validation and Hardware Security through projects, research, and coursework.Tools-Synopsys (Design Compiler, Primetime, ICC, Tetramax ATPG, VCS)-Cadence Virtuoso-Xilinx Vivado IDE, Keil-FPGA-MATLAB-MS (Visio, Word, SharePoint)Technical Languages-Verilog-C/C++-Perl (Basics)-MIPS and ARM AssemblyKey Competencies-Cryptography-Digital Design-Quick Learner-LeadershipKey Achievements:Technical-+Publication- ATPG-based fault Injection Attack on Logic Locking (Accepted - To appear in PAINE conference)+Publication- TAAL: Tampering Attack on Any Key-based Logic Locked circuits (Under Review)+Secured 1st Position in Hardware-Deobfusction Competition at TAME forum held at the University of Florida, 2019.Extra-Curricular-+Initiated a social awareness marathon TESS-RUNN and successfully organized it for 2 years.+Headed the team responsible for organizing the Cultural fest and conducted various robotics workshops.Please contact me at a••••••••@auburn.edu to find out how I might contribute and add value to your next project.

Experience

1. Dft Design Engineer

   Intel

   Nov 2020 — Present · Hudson, MA, US

Education

• Auburn University

  Master of Science - MS (Thesis), Electrical and Computer Engineering

  2018 — 2020

• Pandit Deendayal Energy University

  Bachelor of Technology - BTech, Electrical Engineering

  2014 — 2018