Ayush Jain
Manager Silicon Design Engineering at AMD
- Role
- Manager Silicon Design Engineering at AMD
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Ayush Jain
Specialties: Programming and Software skills: • Languages:System Verilog, VerilogHDL, C/C++, Assembly Language• Verification Methodologies : UVM, VMM• Verification Tools : Cadence, Questa, Axiom• Scripting: Perl• Cadence Design Tools: Virtuoso• Design Tools: Calibre-Layout, DRC, LVS, PEX• Synopsys Design Tools: HSpice, Design Vision• Other Software: MATLAB, CCStudio,T- spice• Processors: ARM Cortex 8A
Experience
Manager Silicon Design Engineering
Jul 2024 — Present · Hyderabad, IN
Education
North Carolina State University
MS, Computer Engineering
2010 — 2012
Vellore Institute of Technology
B.Tech, Electronics and Communication
2005 — 2009
Skills
- C
- Drc
- Matlab
- Arm
- C++
- Verilog
- Processors
- Perl
- Assembly Language
- Systemverilog
- Lvs
- Cadence
- Cadence Virtuoso
- Uvm
- System Verilog
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