Ayush Arpit Garg

About Ayush Arpit Garg

I am a seasoned semiconductor packaging engineer with expertise in 2D, 2.5D, and advanced 3D packaging technologies, including EMIB, Foveros, CoWoS, and hybrid bonded interconnects. In my current role as an OATDF Integration and Yield Engineer at Intel Corporation, I lead the Through Silicon Via (TSV) segment for the Intel 5 product line. I\'m also expanding my focus to include Hybrid Bonded Interconnect (HBI) segments for upcoming Intel products.My experience in TSV integration has honed my ability to collaborate across cross-functional teams to resolve process-related challenges, lead task forces for excursion management, and enhance the robustness of our segment’s operations. My projects have delivered significant improvements, including increased run rates at capacity-constrained modules, cost-saving process innovations, inline defect reductions, and yield improvements at the end of the line. Additionally, I have managed Intel Foundry Services (IFS) product yields for external customers, further diversifying my expertise.Before focusing on TSV and IC Packaging, I served as an R&D engineer in BEOL Wet Etch and Cleans Module, where I drove multiple cost-cutting and run-rate improvement initiatives in a high-volume manufacturing environment. I also contributed to the development of new wet cleans solutions, enabling next-generation technology nodes beyond the Intel 18A process. My contributions have been recognized with several awards throughout my career.

Experience

1. Advanced Packaging Path Finding Integration - Foveros Direct Program (Hybrid Bonding)

   Intel

   Jul 2025 — Present · Hillsboro, OR, US

Education

• The Ohio State University

  Master of Science - MS, Mechanical Engineering

  2013 — 2017

• The Ohio State University

  Doctor of Philosophy - PhD, Mechanical Engineering

  2013 — 2019

• Bhartiya Vidya Bhavan

  All India Senior Secondary Certificate Examination (AISSCE), Physics, Chemistry, Mathematics, Computer Science, and English

  1994 — 2009

• Birla Institute of Technology and Science, Pilani

  B. Tech(Hons.), Mechanical Engineering

  2009 — 2013

• The Ohio State University

  Master of Science - MS, Bioengineering and Biomedical Engineering

  2018 — 2019

Skills

• Ansys
• Matlab
• Microsoft Office
• C++
• Programming
• Autocad
• Data Analysis
• Polarized Light Microscopy
• Cell Culture
• Immunofluorescence
• Western Blotting
• Imagej
• Jmp
• Comsol
• Cleanroom Microfabrication
• Photolithography
• Soft Lithography