Ayush Agarwal

About Ayush Agarwal

Passionate design for testability engineer.Currently working as DFT RTL Implementation engineer at Nvidia.Implementating mentors SSN scan architecture for Nvidia GPUs/SOCsHave knowledge of EDT/SSH architecture to implement SSN at RTL level.Below work is done during M.tech at ITGN: Worked on radiation-hardened memories(latches and SRAM). Proposed three new radiation-hardened robust latches that can tolerate multi-node upset with minimum delay and area overhead.(preparing manuscript for a journal paper - TCAS-1).Done RTL to GDS of 2 stages pipelined processor.(Knowledge of ASIC flow)Good knowledge of Verilog and done verification of different RTL codes using Xilinx Vivado.Performed scan chain insertion and ATPG in multiple blocks using Tessent(DFT).Designed Layout of mirror adder, guard gate, Write driver, and precharge circuit for SRAM and performed DRC, LVS, and PEX on the same using Cadence Virtuoso.passionate about yoga, fitness, food, travel, and spiritualityTools: Synopsys VCS, Xilinx Vivado, Cadence Virtuoso, Mentor Tessent, Innovus, Calibre.Technical skills: Verilog, cadence skill scripting, Basic C and pythonCourses: VLSI Design, Physics of transistors, Microelectronics lab, Analog CMOS IC design, Micro-fabrication

Experience

1. Dft Engineer

   NVIDIA

   Jul 2021 — Present · Bengaluru, IN

   Bengaluru, Karnataka, India

Education

• Hindustan College of science and technology

  B.Tech

  2014 — 2018

• Indian Institute of Technology Gandhinagar

  M.Tech

  2019 — 2021