Avishek Dey
Senior Manager Silicon Design Engineering - Processor Cores Verification at AMD
- Role
- Senior Manager Silicon Design Engineering at AMD
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Avishek Dey
Senior Manager Silicon Design Verification Engineer with overall MTech +~ 15 yrs of experience in design verification.Skills• Developing testplan and verification environment for block and cluster level testbenches• Experience in caches and coherent systems : Protocols : MESI, MOESI• Experience in BUS protocols : AXI4, ACE• Thorough understanding of Object oriented programming.• ASIC Verification Methodology and Verification : Hands-on experience with methodologies - UVM• Experience of Coverage-Driven, Constrained-Random and Assertion Based verification using System Verilog• Simulators used : VCS, NCSim• Scripting Languages expertise : Perl
Experience
Senior Manager Silicon Design Engineering
Apr 2019 — Present · Bengaluru, IN
Education
Indian Institute of Technology, Kharagpur
Master of Technology (M.Tech.), Electrical and Electronics Engineering
2007 — 2009
Jadavpur University
Bachelor of Engineering (B.E.), Electronics and Instrumentation
2002 — 2006
Skills
- Field-Programmable Gate Arrays (Fpga)
- C
- Cpu Verification
- Debugging
- Digital Electronics
- Vhdl
- Application-Specific Integrated Circuits (Asic)
- Embedded Systems
- C++
- Systemverilog
- Verilog
- System Verilog
- Modelsim
- Integrated Circuit Design
- Functional Verification
- Mixed Signal
- Fpga
- Asic
- Uvm
- Computer Architecture
- Vlsi
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