Avinash Yadava
Physical Design Engineer | Versed in Timing Closure |
- Role
- Physical Design Engineer at Chipsolve Technologies Private Ltd
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Avinash Yadava
As a PD Engineer I have developed a strong foundation in VLSI physical design concepts, methodologies, and EDA tools. • Hands-on experience ranges from Synthesis to Place and Route (PNR) and Static Timing Analysis (STA), showcasing my comprehensive understanding of the entire design flow. • Have also applied my skills in TCL scripting to optimize the performance, power & area of the designs.
Experience
Physical Design Engineer
Chipsolve Technologies Private Ltd
Mar 2022 — Present · Hyderabad, IN
Education
Dr. A.P.J. Abdul Kalam Technical University
Bachelor of Technology - BTech
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