Avinash Sharavate
A&MS Layout Design Engineer I
- Role
- a & Ms Layout Design Engineer i at Synopsys Inc
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Avinash Sharavate
Layout EngineerWorked on (DDR/PLL) Samsung (SF2, SF4), TSMC (2nm, 5nm, 7nm, 16nm, 28nm, 40nm, 45nm, 90nm, and 180nm).Designed layout of ESD(Power Clamp, HIA diode, Gated diode, Drain ballasted diode,Core Nmos, RC circuit, mbscr etc), PLL(PFD, Charge Pump, LPF, VCO, Post divider, Loop divider), Analog Driver, BGR, FLASH ADC, DAC, Level Shifter, LDO, Mirror Full Adder, SRAM, Standard Cells, etc.Physical Verification on ICC2 tool in 16nm.worked on High Performance and High Density standard Cells.
Experience
a & Ms Layout Design Engineer i
Jan 2024 — Present · Hyderabad, IN
Education
RV-VLSI and Embedded Systems Design Center
Advance Diploma in ASIC Design
Kavayitri Bahinabai Chaudhari North Maharashtra University, Jalgaon
Bachelor in Engineering
2011 — 2016
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