Avinash Pandey
Formal Verification Engineer at Qualcomm
- Role
- Staff Engineer at Qualcomm
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Avinash Pandey
VLSI Domain SkillsHDLs: Verilog HVL: System VerilogTB Methodology: UVM BasicsScripting Language: Perl C ShellEDA Tool: VCS, SPYGLASS, Bugscope, Jasper-Gold Protocols : AMBA-AHB, APB, CHI
Experience
Staff Engineer
Jan 2024 — Present · Bengaluru, IN
Education
Galgotias university
M.tech, VLSI design
2013 — 2015
Skills
- Fpga
- Asic
- Systemverilog
- Rtl Design
- C++
- C
- Linux
- Modelsim
- Tclsh Shell Scripting
- Tcl
- Cmos
- Eda
- System Verilog
- Very-Large-Scale Integration (Vlsi)
- Verilog
- Sta
- Uvm
- Bash Shell Scripting
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