Avi Debnath

Senior Engineer Analog Verification Methodology @Infineon Technologies

Dresden, DE
MOBILE NUMBERS
+91 *********19

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WORK HISTORY

Oct 2022 — Present

Senior Engineer Analog Verification Methodology @Infineon Technologies

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Owning Spectre/SpectreRF/ADE subflow of a designed AMS reference flow.\\\\n# SKILL Customization of Aanalog Design Environment.\\\\n# Analog/RF design simulation\\\\n# Multi technology simulation\\\\n# Work on collaboration topics with vendors

SKILLS

Synplify Pro E2010.09-1 (Microsemi)Calibre NmdrcRhcsaVerilogLayout DesignPspiceVirtuoso Analog Design Environment (Cadence)CMicrocontrollersSystemverilogCadence Virtuoso Layout EditorActive-Hdl 9.1 (Aldec)Calibre NmlvsC++Calibre RveVirtuoso Schematic Editor (Cadence)Precision_Synthesis Rtl2011a.61 (Mentor Graphics)Matlab

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Avi Debnath — Senior Engineer Analog Verification Methodology at Infineon Technologies in Dresden, DE | Unifers