Avanish Dahiya

About Avanish Dahiya

RTL Design Engineer skilled in Verilog/SystemVerilog, FPGA synthesis, and ASIC front-end design. Experienced in building and verifying digital circuits (ALU, FIFO, cache controllers, UART, pipelined RISC-V cores, and a 64-bit accelerator) with measurable performance gains in both simulation and FPGA prototyping. Strong background in semiconductor devices and nanotechnology, with hands-on expertise in RTL/ASIC design principles, testbench development, and hardware verification.

Experience

1. Jr Hardware Engineer

   Quin

   Dec 2025 — Present · Hyderabad, IN

   The role focuses on embedded hardware validation and firmware integration for sensor-driven devices. Work involves decoding and validating high-rate IMU, impact, and telemetry data over BLE using Python-based analysis pipelines, with attention to bit-level parsing, signed data interpretation, FIFO sequencing, and timestamp integrity. Regular debugging includes identifying data leakage between operating modes, payload inconsistencies, and buffer misalignment by mapping raw hex streams to firmware behavior. Responsibilities also extend to PCB bring-up support, sensor self-test verification, and interface-level debugging across I²C, SPI, and UART, contributing to reliable test workflows and system-level validation.

Education

• SRM Institute of Science and Technology (SRMIST)

  Bachelor of Technology - BTech, Nanotechnology