Avani R.
ASIC Engineering Technical Leader
- Role
- Asic Engineering Technical Leader at Cisco
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Avani R.
17+ years of DFT experience with expertise in various DFT methodologies that includes RTL DFT, Boundary Scan, Scan Insertion, Automatic Test Pattern Generation (ATPG), Memory Built-In Self-Test (MBIST), Test constraints generation and validation, Test pattern validation, controller, implementation, core wrapping, Low power techniques, Synthesis etc.In addition to DFT implementation, worked on different technology nodes from 28nm to 3nm to design DFT architecture, design and development of DFT flows based on customer specific requirements and automations with different toolset – Cadence, Tessent and Synopsys.
Experience
Asic Engineering Technical Leader
Jan 2025 — Present · US
Education
Gujarat University
Bachelor of Engineering (B.Eng.), electronics and communications
2004 — 2008
Dharmsinh Desai University
Master of Technology - MTech, VLSI
2009 — 2011
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