Avadhesh Patel
Formal verification engineer at FVCTO Intel | IIIT Allahabad
- Role
- Formal Verification Engineer at Intel
- Location
- Jhansi, UP, IN
- LinkedIn followers
- 500 followers
About Avadhesh Patel
Formal Verification Engineer at Intel with 3+ years of experience in property verification, connectivity checks, and Compliance Monitor (CompMon) development for complex SoC/IP designs.Skilled in SystemVerilog, SVA, and TCL, with hands-on expertise in JasperGold and Synopsys VC Formal. Focused on catching corner-case bugs early, improving proof convergence, and enabling high-quality, sign-off-ready silicon.
Experience
Formal Verification Engineer
Jan 2023 — Present · Bengaluru, IN
Education
Jawahar Navodaya Vidyalaya (JNV)
Intermediate
2006 — 2013
Government Engineering College, Rewa
Bachelor's Degree
2014 — 2018
Indian Institute Of Information Technology Allahabad
Master's Degree
2020 — 2022
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