Aurodeepta Pattnayak

AI System Architect & Simulation Leader | LLM Perf/Power Modeling | What‑If for System at Scale Projection | CPU/GPU/xPU Full‑System Simulation | Building Trace→Simulation→KPI Transformation Pipeline

Role
Platform Power and Performance Architect at Intel
Location
Hillsboro, OR, US
LinkedIn followers
500 followers

About Aurodeepta Pattnayak

Led (E2E) architecture simulation analysis for next-generation AI hardware systems at hyperscale. • Develop end‑to‑end toolchains to convert execution traces into TaskGraphs for large‑scale simulation; validate & enable these flows across diverse IP features.• Architect & deliver full‑system simulation models (single & multi‑node) integrating performance + power to inform architectural decisions at pre‑silicon.• Perform “what‑if” analyses to explore next‑gen compute architectures—including CPU‑GPU‑AI accelerator integration, memory bandwidth scaling.• Led Power Management & Power Delivery Cross-IP domain Features Integration & Debug for Intel. • Point of Contact for SoC E2E Automation initiatives, infrastructure Enablement of Smart Debug/Triage activities with respect to features stability under various stressful env conditions like Thermal, Voltage, Process & many other HW features/parameters.• Pre-Silicon Test for Post Silicon, Bare-Metal & Synthetic content enablement.• Designed Extensive Test Plan strategy by considering scalability of contents & smart debug, analysis for High volume val.• Domain expertise in Wireless Comm products for PC & Mobile Platforms/ Embedded Sub-systems for Power Management, Firmware, automation tools, and WIFI-BT Coex, Audio Analysis, MMU, Camera, Security & Platform IPs. • Led Technical team for E2E Execution & Debug for Core BT Audio & Coex WIFI-BT Coex Domain.[FW Integration, KPI, Pre-Silicon features] • Architected /Integrated /Delivered Automation Mgn Tools for KPI/Use case for Firmware test. • Feature enablements for connective IPs on Hybrid FPGA Left Shift Environments.• Introduced Crystal Tool for automation reusability/ scalability that adopted by multiple geo execution sites, Received Multiple Department Recognition Awards (Tools & Comp Analysis) for providing the solution for this impactful contribution.Common:++• Influenced the multi-site key SHs, brainstormed with management for new initiatives adding key differentiating value to Intel’s competitive products. • Mentored individuals to give their best with detailed job crafting methodologies for delivering defect-free Firmware features/integrated-to-end products.• Scrumed during phases of Planning/ developing/ Integration/ debug/ validation activities ensuring the key objective of embedded prd lifecycle & Quality.

Experience

  1. Platform Power and Performance Architect

    Intel

    Mar 2023 — Present · US

    Engaged in Power and Performance Projection activities for Intel AI Platforms, focusing on both raw and optimized AI as well as HPC workloads. Conducting debugging and analysis to identify opportunities for optimizing various platform components, with the aim of influencing design decisions strategically. Contributing to the development of an enhanced system for Intel\'s Next-gen product, aligning with both scale-up and scale-out strategies for workloads like generative, LLM, NLP, training, inference, and adv Multimodal LLMs.

Education

  • National Institute of Science and Technology (Autonomous, NBA and NAAC Accredited)

    Bachelor of Engineering, Electrical and Electronics Engineering

  • Ira A. Fulton Schools of Engineering at Arizona State University

    Master in Computer Science, AI & ML, Computer Science

  • Cranes Software International Limited

    Advanced Diploma in Real Time Operating Systems, Computer Software Engineering

  • The Wharton School

    Management Development Program - March 2020, Business Administration and Management, General

  • Khalikote Autonomous College

    CHSE + 2, MPCB

Skills

  • Bluetooth Le
  • Resource Management
  • Multithreading
  • White Box Testing
  • Wifi-Bt Coex
  • Systems Programming
  • Commercialization
  • Jtag
  • Bada
  • Software Architectural Design
  • Firmware Testing
  • Firmware
  • Android Development
  • Android
  • Onsite Coordination
  • Rtos
  • Plm Tools
  • System Testing
  • Embedded Software
  • Uml Tools
  • Team Management
  • Agile Methodologies
  • Embedded Linux
  • Ibm Rational Tools
  • C++
  • Automated Software Testing
  • Embedded Systems
  • Shell Scripting
  • Mobile Interface Design
  • Mobile Applications
  • UI Automation
  • Perforce
  • Debugging
  • Android Framework & Stack
  • Bug Tracking
  • Wireless Technologies
  • Python
  • Bluez
  • Linux
  • Requirements Analysis

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Aurodeepta Pattnayak — Platform Power and Performance Architect at Intel in Hillsboro, OR, US | Unifers