Atul Raghuvanshi

WORK HISTORY

EDUCATION

SKILLS

ABOUT ATUL RAGHUVANSHI

Full chip design analysis and Methodology development at cutting edge process nodes. This includes owning the schematic design, layout supervision, functional verification, timing checks, STA and signing off the design for tapeout. Lead Design Engineering for Custom circuit and Layout design quality assurance, High speed data path design and dynamic circuit design teams. Hard working and supportive lead for custom circuit and layout design. Lead and Custom designer of DRC, LVS, EM, IR, and DFM at block and chip level. Automate design flows using scripting ( Perl/Tcl) as necessary. Acquired experience in all phases of project (e.g. project planning, architecture selection, major parameter estimation, custom design, design documentation, back end design and integration, design validation, quality assurance collaterals coverage, timing closure, functional verification, physical verification etc. Competent in designing High speed and low power circuits and layout, design implementation, floor plan guide to layout designer, validation and testing support. Ability to plan and work independently and co-ordinate with cross-functional teams across geographies. A good understanding of industry EDA tools used in custom and semi-custom implementation of VLSI designs in cutting edge process nodes. A good understanding of electrical, timing and reliability issues in deep sub-micron circuit design. A very good understanding of high speed and low power SRAM design.