Atish Jaiswal

About Atish Jaiswal

Skilled Verification Engineering Leader with 19 years of experience and successfully dealt planning stage to final sign-off of module, sub-system and chip level verification.Skill Sets:UVM, VMM and AVM methodology including coding of all the verification components like Driver, Monitor, Assertions checker, Score-board, Coverage Collector and test-casesSOC Verification on Chips having ARM and Xtensa CPUsZeBu Emulation platform: Verification of Memory controller using UVM methodology.RAL based register programming and verificationLanguage: System Verilog, Verilog, VHDL, CStandards protocols: DDR2, DDR3, LPDDR2, AHB, AXI, PCI, PCIe, I2C, SPI, CANSV Assertion coding and Formal VerificationGLS simulation and debugPre/Post silicon validation of DDR and Video blocksPost Silicon Characterization of DDR interfaceDFT ATPG and MBIST SimulationEDA tools: VCS, QuestaSim, DVE, Verdi, VC-FormalPerl, Shell ScriptingBug Tracking tools: JIRA, Bugzilla Version Control: SVN, GitRegression Management and maintenanceBasic working knowledge of SystemC and Low Power Verification (UPF + MVSIM)Project Management Tool: Project Success Method (PSM), MPPOther tools: Agilent Scope, Thermal ControllerAbility to work across teams from different geography.

Experience

1. Senior Staff Manager

   Marvell Technology

   Jan 2022 — Present · Bengaluru, IN

Education

• RMIT University, Aus

  MS, Microelectronics

  2004 — 2005

• Shivaji University

  BE, Electronics

Skills

• Systemverilog
• Eda
• Asic
• Functional Verification
• Soc
• Vlsi
• Fpga
• Vhdl
• Verilog
• Debugging
• Amba Ahb
• Simulations
• Rtl Design
• Uvm
• Arm
• Embedded Systems
• Semiconductors