Atharva Kulkarni
Design Engineer II @ Cadence Design Systems || Back-End Physical Design
- Role
- Design Engineer Ii at Cadence
- Location
- Pune, IN
- LinkedIn followers
- 500 followers
About Atharva Kulkarni
I am a driven VLSI Design Engineer with 3+ years of professional experience at Cadence Design Systems, specializing in physical design for DDR/LPDDR and GDDR memory interface IPs. My expertise spans from Floorplanning, Placement and Route, Physical Verification and EM-IR Analysis to proficiency in timing closure across advanced technology nodes, including 16nm, 7nm, 5nm, and 4nm. I’ve contributed to multiple successful tapeouts and Design Technology Co-Optimization (DTCO) with data rates up to 8400 Mbps, working with leading foundries like TSMC, Samsung, and Intel.
Experience
Design Engineer Ii
Jul 2023 — Present
Education
Vishwakarma Institute Of Technology
Bachelor of Technology - BTech, Electronics and Communications Engineering
2018 — 2022
Georgia Institute of Technology
Master of Science - MS, Electrical and Computer Engineering
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