Asim Khaniya
Semiconductor Process Engineer | Photolithography & Wafer Processing | EUV/DUV, DOE/SPC, Yield & Defect Reduction | Thin Films & Materials Integration
- Role
- Module Development Engineer at Intel
- Location
- Hillsboro, OR, US
- LinkedIn followers
- 500 followers
About Asim Khaniya
Experienced Process Engineer with a Ph.D. in Physics and 3.5+ years of hands-on…
Experience
Module Development Engineer
Feb 2022 — Present · Hillsboro, OR, US
Developed, optimized, and qualified advanced lithography processes for Intel’s leading technology nodes, enabling successful high-resolution patterning for advanced device architectures (FinFET and GAA). Supported and enabled HVM ramp and technology transfer through seamless execution of new product introductions (NPI) on FEOL layers. Applied SPC, JMP, and DOE methodologies to analyze lithography datasets, driving a reduction in process variability across pilot and production wafers to met module target specs. Led material screening initiatives and DOE-driven development on cost-effective spin-on underlayers for metal oxide resists. Collaborated closely with cross functional teams (Integration, OPC/RET, and Etch teams) to drive mask design optimizations and pattern fidelity improvements, ensuring the alignment to module target specs (MTS) for yield and performance metrics.
Education
University of Central Florida
Doctor of Philosophy - PhD
2020
University of Central Florida
Master of Science - MS
2016
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