Henry Wang
Principal Timing Engineer @Marvell Technology
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WORK HISTORY
Principal Timing Engineer @Marvell Technology
Richmond Hill, ON, CA
EDUCATION
Northeastern University (CN)
Bachelor's Degree, Electrical and Electronics Engineering
SKILLS
ABOUT HENRY WANG
Innovative ASIC Design & Verification Engineer with 20+ years experience in ASIC design, especially in large scale SoC chips integration. Solid knowledge of ASIC design flow and low power design concepts. Expert in design implementation include SoC level integration, logic synthesis, Formal verification, CDC checks, and signoff checks. Experience in SoC level design verification based on System Verilog UVM. Strong leadership skills by effectively managing project schedules, budgets, and resources to meet business objectives.Specialties:• RTL logic synthesis, physical aware and power aware synthesis methodology;• Formal equivalence checking with both Cadence Conformal LEC and Synopsys Formality;• Timing constraints and STA timing closure with Synopsys Primetime;• Extensive knowledge of CDC concepts, and CDC checks with Questa;• Low power design concepts, and implementation with UPF;• Experience with System Verilog UVM verification methodology;• RTL design in Verilog in a SOC and ASIC environment;• AMBA AXI/APB interface protocols;• DDR and DDR PHY interface (DFI) protocols;• Scripting with Perl and TCL.
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