Ashwitha Krishna Kumar

About Ashwitha Krishna Kumar

I started out as a hardware engineer designing FPGAs almost 9 years ago predominantly using Verilog as the RTL language and Xilinx for synthesis, Implementation, Place, and route. After almost two years, I was introduced to Design Verification(DV) and I stuck to it. The part that interests me right from the beginning was how DV involves not just knowledge of the hardware aspect but also the software/IT side like scripting, maintaining tools in a Linux-based infrastructure, etc, Over the years I gained significant experience in bash and some Python scripting. A large part of my work, while being a senior hardware engineer, comprised of creating - test benches, test plans, test cases, regressions, debugging test failures, and fixing them by closely working with the design engineers. After becoming a technical lead we transitioned to using UVM(Universal Verification Methodology) as our primary verification language. Through this, I was able to gain considerable experience working with Cadence VIPs, System Verilog, constraint Random verification, Code, and Functional Coverage. Apart from all the DV skills, I also had the opportunity to not just use the Cadence Xcelium and vManager tool but also install and keep them updated. DV has become my passion and I hope to make many more strides as my career progresses.

Experience

1. Design Verification Lead - Flashsystems

   IBM

   May 2019 — Present · Houston, TX, US

Education

• Anna Adarsh Higher Sec School

  High School, Science

  2002 — 2005

• Illinois Institute of Technology

  Master of Science, Electrical Engineering - Computer & Microelectronics

  2010 — 2012

• SASTRA University

  Bachelor Of Technology, Electronics & Communication Engineering

  2005 — 2009