Ashutosh Rane
Physical Design Engineer, (Synthesis, PNR, STA, EM/IR, PV, LEC CLP checks)
- Role
- Senior Staff Engineer at Samsung Semiconductor
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Ashutosh Rane
Physical Design Engineer with 12 years of design implementation experince. Working on physical Design of complex design systems. Hands on knowledge of synthesis to GDS design flow.Strong Skills: CPU Systems/ Arm Cores/Automotive chip designs. Skilled in synthesis, Floorplanning, Placement, CTS: MSCTS, conventional CTS, Timing closure, LEC/CLP, Static and Dynamic IR Analysis in Redhawk, Power Estimation using PTPX. PV closure using calibre for DRC LVS. Handson knowledge of tools like Innovus, Fusion Compiler, Tempus,PT, PTPX, Calibre.
Experience
Senior Staff Engineer
Mar 2024 — Present · Bengaluru, IN
Education
KIT’s College of Engineering, Shivaji University Maharashtra
Bachelor's degree, Electronics Engineering
National Institute of Technology Calicut
M. Tech.(microelectronics and VLSI design), Analog IC design, Digital IC design, Testing and verification, MOS modelling, VHDL,
2009 — 2011
Skills
- Simulation
- Vlsi
- Analog Circuit Design
- Cmos
- Cadence Virtuoso
- Digital Electronics
- Ic
- Analog
- Very-Large-Scale Integration (Vlsi)
- Spectre
- Verilog
- C
- Physical Design
- Vhdl
- Circuit Design
- Rtl Design
- Asic
- Integrated Circuit Design
- Analog Design
- Digital Design
- Matlab
- Xilinx
- Silicon
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.