Ashot Martirosyan

About Ashot Martirosyan

IC Layout Design Engineer with over 18 years of experience in RF, Analog and Mixed Signal ICs, I/O and St. Cell Libraries, Special IOs in CMOS/SOI 0.5um-28nm.•Long years expertise in techniques of Floor planning and top-level routing (matching, isolation/shielding), Standard Cell creation of CMOS and PCELL devices.•Definition of IO library cell’s set in dependence to functionality and ESD protection methodology. •Done layout for high speed complete Receiver and Driver Chip including IO pads and their ESD circuitry. •Theoretical knowledge of CMOS devices\' physics and layout dependent parameters•Expertise in layout editing tools: Analog Master/Leda Systems, Virtuoso LE/ XL, Synopsys Custom Designer LE SE, Synopsys Cosmos LE SE•Strong skills of Layout Physical Verification - DRC/LVS/ANT•Excellent communication and teamwork skills, creative and fast learning•Strong sense of personal responsibilitySpecialties: •Knowledge of ANALOG, DIGITAL and RF layout design. •Skilled in various layout design editing tools. •Skilled in various layout design verification tools(Mentor Graphics/Calibre, Synopsys/Hercules Cadence/Assura). •Basic experience in auto router tools(Synopsys/Astro, Cadence /Appolo). •Unix, Sun, WIndows OS. •Basic experience in scripting.

Experience

1. Layout Engineer

   Apple

   Mar 2020 — Present

Education

• State University of Engineering of Armenia

  BS, Automated Systems for Information Processing and Control

  1997 — 2001

• State Engineering University of Armenia

  MS, Informatics and Computer Systems

  2001 — 2003

Skills

• Vco
• Lvs
• Cadence
• Ic
• Analog
• Layout
• Unix
• Rf
• Scripting
• Debugging
• Mixed Signal
• Windows
• Physical Verification
• Dac
• Analog Circuit Design
• Semiconductors
• Design Rule Checking (Drc)
• Drc
• Cmos
• Asic
• Pll
• Usb
• Lna
• Sun
• Layout Versus Schematic (Lvs)
• Physical Design
• Linux
• Virtuoso
• Perl
• Eda
• Cadence Virtuoso
• Vlsi
• Verilog
• Esd Control
• Ic Layout
• Electronics
• Functional Verification