Ashok Tummala

WORK HISTORY

EDUCATION

SKILLS

ABOUT ASHOK TUMMALA

Lead Architect, Micro-Architect and Designer for ARM coherent interconnect/Fabric IP CMN and CCN• Areas of expertise include H/W managed cache coherency, On/Off-chip interconnect standards (CHI, AXI, ACE, PCIe, CXL, CCIX), High Speed I/O, memory side concepts including transaction ordering rules (ARM ISA, CHI, AXI, PCIe etc.), memory types/attributes guarantees, Exclusives/Atomics etc. System Architecture concepts including I/O virtualization (SMMU, DVMs), interrupt handling, error handling (RAS). Networking concepts including layered architectures, flow control, deadlock free routing. • Key contributor to ARM AMBA protocols (CHI, CHI C2C, CXS, ACE-L, AXI). Involved in ground up definition of CHI, CHI C2C, CXS protocols• Key driver of “PCIe, CXL and CCIX enablement effort in CMN based systems” for both Host and Device implementations. In depth knowledge of these industry standards including the full H/W and S/W stack• Architect and micro-architect of optimized common CMN gateway used for multichip, multiple protocol communication (CMN-to-CMN SMP, CXL, CCIX). Architect of CMN’s Coherent Multi-chip Link (CML) Data Link Layer split definition, which decouples the underlying lower link layer and PHY from the protocol it’s carrying. This definition enables CMN’s multi-chip link for multiple protocol communication and can use different PHY technologies (Die-to-Die which include OpenHBI, XSR, BoW etc, socket-to-socket which includes CXL, PCIe etc.)• Lead micro-architect and designer of various protocol blocks on CMN and CCN interconnects including I/O bridges (AXI/ACE-L CHI), CCIX/CXL gateway block. This involves ground up definition and design of these protocol blocks. Involved in full development cycle of these units, from architecture, micro-architecture definition, to design, performance analysis, timing closure to delivery of these units to CMN/CCN customers