Ashok Nandigam

About Ashok Nandigam

20+ years of experience in successful implementation and verification of test…

Experience

1. Senior Member of Technical Staff(Dft)

   AMD

   Mar 2016 — Present

   Project Lead for multiple chips. • Responsible for overall execution (integration, verification, scan implementation, gate level verification, DFT timing and tester pattern generation and validation) of DFT of SoC. • Driving a team of 15-20 members teams related to various DFT functions throughout project execution and post silicon activities. • Working with various functions on improving SCAN architecture enabling latest features to reduce pattern count and improve coverage targets. • Have good experience in handling DFT architecture w.r.to various voltage and power domains. • Worked with consultants from various companies to make sure we can execute projects smoothly. Have been involved on project and resource planning. • Worked extensively on developing timing constraints for all DFT functions at SOC level. • Developed sanity scripts to valid the timing constraints and unintentional exceptions. • Review timing checks and timing violations. Fix the constraints and generating exceptions. • Worked with various IP teams to get timing constraints and validate QOR. • Generating ATPG patterns (intest/extest, Compression, Bypass) and broadcasting technique for identical codecs. • Post silicon debug support which includes ATE and HDT(AMD debug unit) platform bringup. • Worked extensively with Product Engineering team on pattern delivery and silicon debug for various projects. • Have got spotlight awards for multiple projects.

Education

• C-DAC

  Post Graduation Diploma, VLSI

  2004 — 2005

• Jawaharlal Nehru Technological University

  B.Tech, Electronics and Communication Engineering

  2000 — 2004

Skills

• Analog Mixed Signal
• Ncsim
• Specman
• Asic
• Formal Verification
• Atpg
• Bist
• Modelsim
• Verilog
• Vlsi
• Dft
• Soc