Ashish K.

About Ashish K.

I am an FPGA & ASIC Design Engineer with 2.3 years of hands-on experience in 5G…

Experience

1. Sr Asic Rtl Design Engineer

   IndieSemiC

   Feb 2025 — Present · Ahmedabad, IN

   1) Led a team of 5 engineers, managing end-to-end design, documentation, and FPGA bring-up of a custom processor.2)Designed and implemented a single-core processor from scratch capable of running FreeRTOS applications.3)Worked on both hardware (RTL design, FPGA prototyping) and embedded software (driver development).4)Verified designs with 10k+ binaries, generating.hex and.elf files for software applications.5)Developed Tcl scripts for automated testing, testbenches, implementation, and bitstream generation.6)Tested and validated on Xilinx Artix-7 FPGA; performed synthesis and STA using Cadence Genus, Tempus, and lint checks with SpyGlass.7)Integrated and tested APB-based IPs (SPI, UART, I2C, Timer); built GPIO LED control and UART communication with PuTTY.8)Utilized ILA and VIO for real-time FPGA debugging and signal monitoring.//-//plan: 1. NPU integration 2.FPU 3. PIPELINE 4. Go for linux booting 5. 256-AES Protections