Ashish Agarwal

About Ashish Agarwal

More than 17 years of extensive experience in Block-level to SoC verification of various ASICs with different level of complexities and in Verification-IP development Specialties- Worked extensively on different DDR, LPDDR and NVMe standards, Memory-controller, AXI 3.0 and DFI2.1 interfaces- Involved in the development of DDR2/3, LPDDR, USB3.0 and ATAPI Verification IPs in HVLs like \'e\' and System Verilog-Functional Verification of Module to System Level ASICs- Hands on experience of working with various tools like Specman, Incisive Unified Simulator (including NC-Sim, Simvision, etc.), QuestaSim, Incisive Enterprise Manager, Enterprise Planner and many more.MMor

Experience

1. Dv

   Arm

   Sep 2023 — Present · GB

   Collaborate with other functional verticals such as Image Quality, Technology and model teams for managing dependencies and seamless handover.Manage verification process improvements and standardization for reuse.Developed UVM-based testbench at both core and top-level for Image Processing Modules.Automated regression testing and implemented continuous integration practices.

Education

• National Institute of Technology Calicut

  B.Tech, EEE

  2002 — 2006

Skills

• Usb
• Simulation
• Ddr
• Asic
• Uvm
• Axi
• Eda
• System on a Chip (Soc)
• Open Verification Methodology
• Hardware
• Rtl Coding
• Arm Architecture
• Systemverilog
• Soc
• Modelsim
• Ddr2
• Functional Verification
• Verilog
• Ncsim
• Very-Large-Scale Integration (Vlsi)
• Simulations
• Universal Verification Methodology (Uvm)
• Service Provider Interface (Spi)
• Spi
• Application-Specific Integrated Circuits (Asic)
• Vlsi
• Hardware Verification
• Arm
• Ddr3
• Specman