Ashish Srivastava

About Ashish Srivastava

Objective:To build a career in a VLSI company which will help me to make a strong contribution to Organization goals through my academic and technical skills.TECHNICAL SKILLS-•Through the knowledge of Physical Design Concept from anything ranging Between RTL toTap out.•Familiar with ASIC Back-end Design Methodology.•Comprehensive understanding of Methodology of Floor- planning, Place and Route, Timing closure, Physical Design, Chip Level Timing (STA) and CTS.LANGUAGES-Programming Skills: HDL (Hardware description language)- Verilog, System Verilog.Scripting languages- Perl, shell.Other languages- Basic of C, C++. EDA TOOLS (DIGITAL DESIGN)-Synthesis Tool- NC launch (Cadence ).Pre Layout Simulator - NC Sim(Cadence), Modelsim (Altera).Post Layout Simulation, LVS/DRC- Virtuoso Schematic Editor,Virtuoso Layout Suite(Cadence).STA - Encounter RTL complier (Cadence), NC launch (Cadence).Backend - SOC Encounter(Cadence).Parasitic Extraction Tools - Assura RCX (Cadence).FPGA Boards-Altera DE2 board.

Experience

1. R & d Engineer Ic Design 4

   Broadcom

   Nov 2023 — Present · Bengaluru, IN

Education

• Vellore Institute of Technology

  Master of Technology (M.Tech.), VLSI -Design

  2012 — 2014

Skills

• Field-Programmable Gate Arrays (Fpga)
• Physical Design
• Cmos
• Static Timing Analysis
• Application-Specific Integrated Circuits (Asic)
• Perl
• Systemverilog
• Verilog
• Rtl Design
• System Verilog
• Modelsim
• Integrated Circuit Design
• Functional Verification
• Perl Script
• Logic Design
• Fpga
• Asic
• Shell Scripting
• Cadence